Logic Design of a Fast Circuit for Iterative Additions in Redundant Hybrid
نویسندگان
چکیده
Repeated modular additions and overflow detection are possible in redundant hybrid number systems (RHNS). In this paper a circuit is proposed that implements the overflow-detecting procedure in such systems and allows a mean addition time of about 10.5 gate delays for numbers having a magnitude order normally distributed in the range [−233, 233 − 1], versus a 14 gate delay required by 32-bit CLA adders.
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ورودعنوان ژورنال:
- Comput. J.
دوره 41 شماره
صفحات -
تاریخ انتشار 1998